Intel 4 heralds the disaggregated future of mobile CPUs | Albiseyler

Intel 4 heralds the disaggregated future of mobile CPUs

During an opening keynote at the Intel Innovation event in San Jose, CEO Pat Gelsinger revealed a number of details about the upcoming Meteor Lake client platform. Intel’s Meteor Lake marks the beginning of a new era for chipmakers as they move away from the messy Intel 7 node and introduce their Foveros 3D packaging with EUV lithography for their upcoming client mobile platform. For the first time, Meteor Lake uses a tiled, segmented chiplet architecture for its client-facing processors, changing the very nature of Intel’s consumer chips going forward. And according to Intel, all these changes have allowed them to bring significant progress to the mobile market.

Intel’s first chiplet-based consumer processor divides the common functions of a modern CPU into four separate tiles: compute, graphics, SoC and I/O tiles. Within the compute tile is a new pair of cores, a P-core called Redwood Cove and a new E-core called Crestmont. Both of these cores promise IPC gains over their previous counterparts, but perhaps the most interesting inclusion is a new type of E-core built right into the SoC tile, which Intel calls a “Low Power Island.” These new LP E-cores are designed with the idea that light workloads and processes can be offloaded to more power intensive compute tiles and offloaded to more efficient tiles with lower power consumption. Other major additions include the new Intel Neural Processing Unit (NPU), which resides in the SoC tile and is designed to bring on-chip AI capabilities for workloads and inference, paving the way for the future.

With Meteor Lake, Intel is trying to get into a more competitive position in the mobile market with significant improvements in the compute core hierarchy, Intel Xe-LPG Arc graphics tiles that will boost the integrated graphics capabilities, and an NPU that adds various AI Benefits. Meteor Lake also sets the scene for Intel and modular disaggregation, with the Foveros 3D package set to become a mainstay of Intel’s processor plans going forward, with the Intel 4 process making its debut and acting as a springboard for what will become Intel’s next pillar. node in all its factories, Intel 3.

Intel Meteor Lake: Intel 4 using Foveros 3D Packaging

Intel’s Meteor Lake architecture isn’t just another iteration in a long line of processor improvements; according to the company, this is a revolutionary leap forward. Executive Vice President and General Manager of Intel’s Client Computing Group (CCG), Michelle Johnston Holhaus, spoke eloquently at Intel’s Tech Tour 2023 in Penang, Malaysia that Intel has reached an inflection point in their client roadmap. Revealing more details about Meteor Lake at the Intel Technology Tour in Malaysia, the architecture is a step up from current client processors in terms of performance as we progress through Intel’s “5 Nodes in 4 Years” plan.

Meteor Lake is built on Intel’s disaggregated architecture, promoted by Foveros packaging. This is designed to optimize both performance and energy efficiency. The architecture itself consists of four unique and distinct tiles connected using Intel Foveros 3D packaging technology. This includes the compute tile, which is built on Intel 4, while the graphics tile is built on TSMC’s N5 node. The other two tiles that Intel implements in Meteor Lake are the SoC tiles that act as a central hub through an embedded NOC. This is the first time Intel has used Network-on-Chip (NOC) on their client processors, a simplified approach to NOC on their existing Agilex FPGAs. While on Agilex the NOC is individualized into various NoC targets and switches within the NoC substructure, on Meteor Lake it directly connects to the I/O fabric via the IoC, which then goes into the I/O fabric. The NOC itself is directly connected to the graphics tile, compute tile, and other components in the SoC.

This modular approach enables a mature and scalable power management architecture that supports disaggregation and allows each tile to operate independently. This disaggregated design prioritizes performance by negating bandwidth throttling through things like I/O on a monolithic design and focusing on increased energy efficiency. Perhaps the most notable element of disaggregation is that Intel can select specific silicon processes for each tile and is not limited to a single process node. In addition to the energy efficiency and package area benefits of the tiled architecture, it is cheaper for Intel to produce CPUs with fewer masks via EUV, but this allows Intel to scale new IP to future products while maintaining the same base, which is another cost saving factor (for Intel).

Compared to the mobile Raptor Lake, which was made using Multi-Chip Packaging (MCP), Meteor Lake uses Foveros BGA packaging and offers a low-power die-to-die interconnect, for which Intel has confirmed a small power penalty between 0.15 and 0.3 picojoules. (pJ) communicating from tile to tile. Advantages of Foveros include better customizability with tiles, allowing Intel to make chips and implement specific tiles and IP depending on chip class, etc., low power with more I/O or high end tiles with all the latest gadgets and gizmos. With the Intel 7 node not as viable as they’d hoped, Intel is promising higher wafer yields on the Intel 4, which uses less wafer space for logic-based silicon.

Power management is done using a scalable power management system that supports the independent operation of each tile. Coordination between multiple PMCs and system software is designed to be optimized for different workloads. Intel’s Meteor Lake architecture also introduces a new scalable architecture to improve energy efficiency and expand bandwidth in previously problematic areas such as I/O.

As for the multiple power controllers within the Meteor Lake architecture, Intel has integrated independent power management controllers in each of the tiles. As part of the disaggregation of using Foveros, each tile must be independently power managed, and the use of PMCs on the NOC, I/O fabric, as well as on each tile allows power management to be agnostic to the number of cores per package.

Meteor Lake itself represents a monumental architectural shift, not just an incremental update, as it represents the most significant architectural transformation in client processors in four decades. That’s because it’s the first client processor to be built using chips instead of a monolithic design. The architecture is designed to be the cornerstone of Intel’s strategy to drive PC innovation for the next decade. Looking at some of the finer details of Intel’s architecture, Meteor Lake uses Intel’s Foveros packaging technology, which uses 3D chip stacking to address the pitfalls of traditional 2D chip layouts.

As we can see from Intel’s Hot Chips 2023 announcement above, the top and bottom layers have bumps to interconnect each die. The use of Foveros FDI packaging offers a low-voltage CMOS (Complementary Metal Oxide Semiconductor) interface, which means that the power circuits can be operated at lower voltages and therefore at lower power. Another advantage of FDI is both synchronous and asynchronous signaling, which means that the signal transmission can handle full-duplex data blocks.

The design of the Meteor Lake SoC includes a package substrate that is the basis for seating the base tile, which uses Foveros Die Interconnect (FDI). The motherboard has a pitch of 36 ┬Ám with metal lamination and an operating power of 0.15 to 0.3 pJ at 2 GHz; this may fluctuate or vary with voltage, amps and frequency. Since this is a basic tile, it is not the active chiplet itselfIts sole function is to serve as the foundation for all the various logic and metal layers for the chips be placed on.

Intel’s Meteor Lake architecture composition uses four different tiles to create Meteor Lake CPUs. This includes Compute, SoC, GPU and I/O tiles, all with different uses, capabilities and flexibility when it comes to IP. Power management has also been improved. Due to disaggregation using Intel Foveros packaging technology, each tile in Meteor Lake requires its own power management. Intel’s solution is a hierarchical power management system that uses power management controllers on the NoC, the IO, and each individual tile.

Over the next few pages, we’ll provide a look at each of the four boards, what each board brings to the table, and more about the various technologies that are driving innovation through Meteor Lake.

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